ESD protection circuit and display panel using the same

ABSTRACT

An ESD protection circuit for low temperature poly-silicon thin film transistor panel and a display panel using the same. The feature of the ESD protection circuit comprises an ESD detection circuit disposed between a first power line and a second power line, for outputting an enable signal when an ESD event occurs in the first power line; and a discharge device having a control terminal coupled to the output of the ESD detection circuit, for providing a discharge path between the first and second power lines when the control terminal receives the enable signal.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an electrostatic discharge (ESD)protection circuit and its application, and in particular relates to anESD protection circuit for thin film transistor (TFT) liquid crystaldisplay (LCD) panel and a display panel using the same for ESDprotection.

[0003] 2. Description of the Related Art

[0004] ESD management is an increased reliability issue in complementarymetal oxide semiconductor (CMOS) integrated circuits (ICs) due totechnology scaling and high frequency requirements. For example in radiofrequency (RF) ICs, on-chip ESD protection design suffers from severallimitations, such as low parasitic capacitance, constant inputcapacitance, insensitivity to substrate coupling noises, and robust ESDprotection. In order to fulfill these requirements, diodes are commonlyused for ESD protection in I/O circuits.

[0005] In the above, the power-rail ESD clamp circuit is important inimproving the ESD protection in IC products. As well, the power-rail ESDclamp circuit must be triggered efficiently during ESD events.

[0006] TFT LCD display panels accumulate significant charge in themanufacturing process, for example low temperature poly-silicon (LTPS)process, posing danger to transistors of internal driving circuit.

[0007] In general, ESD protection circuits for LTPS TFT panels, use adiode between V_(DD) and V_(SS) lines. The diode is turned on, providinga discharge path for a transient current when ESD events occur in theV_(DD) line or the V_(SS) line. However, a bias still exist between theV_(DD) and V_(SS) lines and generates discharge effect in internalcircuits. Thus, the above method is unable to enhance the ESDprotection.

SUMMARY OF THE INVENTION

[0008] It is therefore an object of the present invention to provide anESD protection circuit for TFT LCD display panel, especially for lowtemperature poly-silicon (LTPS) TFT LCD display panel and a displaydevice using the same.

[0009] The ESD protection circuit comprises first and second powerlines, an ESD detection circuit, and a discharge device. The ESDdetection circuit is connected between the first power line and thesecond power line. The ESD detection circuit outputs an enable signalwhen an ESD event occurs in the first power line. The discharge devicehas a control terminal (CTR) coupled to the output terminal of the ESDdetection circuit, a first terminal coupled to the first power line, anda second terminal coupled to the second power line. The discharge devicethereby provides a discharge path when the control terminal receives theenable signal.

[0010] The ESD detection circuit comprises a resistor, a capacitor, afirst thin film transistor, and a second thin film transistor. Theresistor has a first terminal coupled to the first power line. Thecapacitor has a first terminal coupled to a second terminal of theresistor and a second terminal coupled to the second power line. Thefirst thin film transistor has a gate coupled to the second terminal ofthe resistor, a source coupled to the first power line, and a draincoupled to the control terminal (CTR). The second thin film transistorhas a gate coupled to the second terminal of the resistor, a sourcecoupled to the second power, and a drain coupled to the drain of thefirst thin film transistor.

[0011] In addition, the display panel with the ESD protection circuitcomprises a plurality of gate lines, a plurality of data lines, aplurality of display units, a gate driver, a data driver, at least onefirst power line and at least one second power line, and at least an ESDprotection circuit disposed between the first and second power lines.The main feature of the ESD protection circuit in the display panel isthe same as that described above.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention can be more fully understood by thesubsequent detailed description and examples with reference made to theaccompanying drawings, wherein:

[0013]FIG. 1 shows a TFT LCD display panel with ESD protection circuitof the present invention;

[0014]FIG. 2 shows a first embodiment of the ESD protection circuit;

[0015]FIG. 3 shows a second embodiment of the ESD protection circuit;

[0016]FIG. 4 shows a third embodiment of the ESD protection circuit;

[0017]FIG. 5 shows a fourth embodiment of the ESD protection circuit;

[0018]FIG. 6 shows a fifth embodiment of the ESD protection circuit.

DETAILED DESCRIPTION OF THE INVENTION

[0019]FIG. 1 shows a TFT display panel with ESD protection circuit 10 ofthe present invention. The display panel comprises a gate driver 1, adata driver 2, a display array 3, and an electrostatic discharge (ESD)protection circuit 10 disposed between a first power line V_(DD) and asecond power line V_(SS).

[0020] The display array 3 comprises a plurality of gate lines G1˜Gn, aplurality of data lines D1˜Dm, and a plurality of display units 30˜33(only 4 units depicted in FIG. 1). Each of the display units comprises athin film transistor Mx, which can be LTPS TFT or amorphoussilicon(a-Si) TFT, and connected to the corresponding gate lines anddata lines. The gate driver 1 outputs scan signals to gate lines G1˜Gn.The data driver 2 outputs video signals to data lines D1˜Dm.

[0021] The electrostatic discharge (ESD) protection circuit 10 is usedto provide a discharge path when an ESD event occurs in the first powerline V_(DD) during fabricating the TFT LCD display panel, thus providingESD protection to the display panel. The ESD protection circuit 10 isdescribed in detail as follows.

[0022]FIG. 2 shows one embodiment of the ESD protection circuit. The ESDprotection circuit 10, disposed between the first power line V_(DD) andthe second power line V_(SS), comprises an ESD detection circuit 11, anda discharge device 12. The ESD detection circuit 11 is connected betweenthe first power line V_(DD) and the second power line V_(SS). When theESD event occurs in the first power line V_(DD), the ESD detectioncircuit 11 outputs an enable signal. The discharge device 12 has acontrol terminal CTR coupled to the output of the ESD detection circuit11, a first terminal E1 coupled to the first power line V_(DD), and asecond terminal E2 coupled to the second power line V_(SS). Thedischarge device 12 provides a discharge path for the ESD when thecontrol terminal CTR receives the enable signal.

[0023] In FIG. 2, the ESD detection circuit 11 comprises a resistor R, acapacitor C, a first P-type thin film transistor M_(p1), and a secondN-type thin film transistor M_(N1). The resistor R has a first terminalcoupled to the first power line V_(DD). The capacitor C has a firstterminal coupled to a second terminal of the resistor R and a secondterminal coupled to the second power line V_(SS). The first P-type thinfilm transistor M_(P1), has a gate coupled to the second terminal of theresistor R, a source coupled to the first power line V_(DD), and a draincoupled to the control terminal CTR of the discharge device 12. Thesecond N-type thin film transistor M_(N1) has a gate coupled to thesecond terminal of the resistor R, a source coupled to the second powerV_(SS), and a drain coupled to the drain of the first N-type thin filmtransistor M_(P1).

[0024] The discharge device 12 is an N-type thin film transistor M_(N2)with a gate (the control terminal CTR) coupled to the drain of the firstP-type thin film transistor M_(p1), a source coupled to the first powerline V_(DD), and a drain coupled to the second power line V_(SS).

[0025] The resistor R and capacitor C define a delay constant exceedingthe duration of the ESD pulse (generally about several hundrednano-seconds). When the ESD pulse (e.g. with positive voltage) occurs inthe first power line V_(DD) during fabricating process, the voltage atthe point Vx is less than that of the ESD pulse. Therefore, a voltagedifference between the gate and source of the PMOS transistor M_(P1) isinduced. When the voltage difference exceeds the threshold voltage ofthe PMOS transistor Mp₁, the PMOS transistor M_(P1) turns on and pullsup the voltage at the control terminal CTR (outputs the enable signal),whereby the NMOS transistor M_(N2) is turned on to provide a dischargepath for dissipating the ESD current from the first power line V_(DD) tothe second power line V_(SS).

[0026]FIG. 3 shows a second embodiment of the ESD protection circuit.The capacitor C is a third N-type thin film transistor M_(N3) with agate coupled to the second terminal of the resistor R and a source anddrain coupled to the second power line V_(SS).

[0027]FIG. 4 shows a third embodiment of the ESD protection circuit. TheESD detection circuit 11 b comprises a resistor R and a capacitor C. Theresistor R has a first terminal coupled to the first power line V_(DD).The capacitor C has a first terminal coupled to a second terminal of theresistor R and a second terminal coupled to the second power lineV_(SS). The discharge device 12 b is a P-type thin film transistor MP₂with a gate coupled to the second terminal of the resistor R, a sourcecoupled to the first power line V_(DD), and a drain coupled to thesecond power line V_(SS).

[0028] Similarly, the resistor R and capacitor C define a delay constantexceeding the duration of the ESD pulse. When the ESD pulse occurs inthe first power line V_(DD) during fabricating process, the voltage atcontrol terminal CTR is less than that of the ESD pulse. Therefore, avoltage difference between the gate and source of the PMOS transistorM_(P2) is induced. When the voltage difference exceeds the thresholdvoltage of the PMOS transistor MP₂, the PMOS transistor MP₂ turns on toprovide a discharge path for dissipating the ESD current from the firstpower line V_(DD) to the second power line V_(SS).

[0029]FIG. 5 shows a fourth embodiment of the ESD protection circuit.The ESD detection circuit 11 c comprises a capacitor C and a resistor R.The capacitor C has a first terminal coupled to the power line V_(DD).The resistor R has a first terminal coupled to a second terminal of thecapacitor C and a second terminal coupled to the power line V_(SS). Thedischarge device 12 c is an N-type thin film transistor M_(N4) that hasa gate coupled to the second terminal of the capacitor C, a sourcecoupled to the power line V_(SS), and a drain coupled to the power lineV_(DD).

[0030] Similarly, the resistor R and capacitor C define a delay constantexceeding the duration of the ESD pulse. When the ESD pulse (e.g. withnegative voltage) occurs in the power line V_(SS) during fabricatingprocess, the voltage at control terminal CTR is higher than that of theESD pulse (at the power line V_(SS)). Therefore, a voltage differencebetween the gate and source of the NMOS transistor M_(N4) is induced.When the voltage difference exceeds the threshold voltage of the NMOStransistor M_(N4), the NMOS transistor M_(N4) turns on to provide adischarge path for dissipating the ESD current from the power lineV_(SS) to the power line V_(DD).

[0031]FIG. 6 shows a fifth embodiment of the ESD protection circuit. TheESD detection circuit 11 d comprises a capacitor C, a resistor R, and aninverter 13. The capacitor C has a first terminal coupled to the powerline V_(DD). The resistor R has a first terminal coupled to a secondterminal of the capacitor C and a second terminal coupled to the powerline V_(SS). The inverter 13 has an input terminal coupled to the secondof the capacitor C and a second output terminal coupled the controlterminal CTR. The discharge device 12 d is a P-type thin film transistorMP₃ with a gate coupled to the second output terminal of the inverter13, a source coupled to the power line V_(DD), and the drain couples tothe power line V_(SS). In this embodiment, the inverter 13 and the PMOStransistor M_(P3) jointly perform the same function as the NMOStransistor M_(N4) depicted in FIG. 5.

[0032] While the invention has been described by way of example and interms of the preferred embodiments, it is to be understood that theinvention is not limited to the disclosed embodiments. To the contrary,it is intended to cover various modifications and similar arrangements(as would be apparent to those skilled in the art). Therefore, the scopeof the appended claims should be accorded the broadest interpretation soas to encompass all such modifications and similar arrangements.

What is claimed is:
 1. An electrostatic discharge (ESD) protectioncircuit for thin film transistor display panel comprising: a first powerline; a second power line; an ESD detection circuit connected betweenthe first power line and the second power line, for outputting an enablesignal when an ESD event occurs in the first power line; and a dischargedevice having a control terminal coupled to the output of the ESDdetection circuit, a first electrode coupled to the first power line,and a second electrode coupled to the second power line, for providing adischarge path between the first and second power lines when the controlterminal receives the enable signal.
 2. The electrostatic dischargeprotection circuit as claimed in claim 1, wherein the ESD detectioncircuit comprises: a resistor having a first terminal coupled to thefirst power line; and a capacitor having a first terminal coupled to asecond terminal of the resistor and a second terminal coupled to thesecond power line.
 3. The electrostatic discharge protection circuit asclaimed in claim 2, wherein the discharge device is a P-type thin filmtransistor with a gate coupled to the second terminal of the resistor, asource coupled to the first power line, and a drain coupled to thesecond power line.
 4. The electrostatic discharge protection circuit asclaimed in claim 1, wherein the ESD detection circuit comprises: acapacitor having a first terminal coupled to the first power line; and aresistor having a first terminal coupled to a second terminal of thecapacitor and a second terminal coupled to the second power line.
 5. Theelectrostatic discharge protection circuit as claimed in claim 4,wherein the discharge device is an N-type thin film transistor with agate coupled to the second terminal of the capacitor, a source coupledto the second power line, and a drain coupled to the first power line.6. The electrostatic discharge protection circuit as claimed in claim 4,wherein the ESD detection circuit further comprises an inverter disposedbetween the second terminal of the capacitor and the control terminal ofthe discharge device.
 7. The electrostatic discharge protection circuitas claimed in claim 6, wherein the discharge device is a P-type thinfilm transistor with a gate coupled to the output of the inverter, asource coupled to the first power line, and a drain coupled to thesecond power line.
 8. The electrostatic discharge protection circuit asclaimed in claim 1, wherein the ESD detection circuit comprises: aresistor having a first terminal coupled to the first power line; acapacitor having a first terminal coupled to a second terminal of theresistor and a second terminal coupled to the second power line; a firstP-type thin film transistor having a gate coupled to the second terminalof the resistor, a source coupled to the first power line, and a draincoupled to the control terminal; and a second N-type thin filmtransistor having a gate coupled to the second terminal of the resistor,a source coupled to the second power, and a drain coupled to the drainof the first P-type thin film transistor.
 9. The electrostatic dischargeprotection circuit as claimed in claim 8, wherein the discharge deviceis an N-type thin film transistor with a gate coupled to the output ofthe ESD detection circuit, a source coupled to the first power line, anda drain coupled to the second power line.
 10. The electrostaticdischarge protection circuit as claimed in claim 9, wherein thecapacitor is a third N-type thin film transistor with a gate coupled tothe second terminal of the resistor and a source and drain coupled tothe second power line.
 11. A display panel with ESD protection circuit,comprising: a display array comprising a plurality of gate lines, aplurality of data lines, and a plurality of display units respectivelyconnected to corresponding data lines and corresponding gate lines; agate driver; a data driver; at least a first power line; at least asecond power line; and at least an electrostatic discharge (ESD)protection circuit disposed between the first and second power lines;wherein the ESD protection circuit comprises an ESD detection circuitconnected between the first power line and the second power line, foroutputting an enable signal when an ESD event occurs in the first powerline; and a discharge device having a control terminal coupled to theoutput of the ESD detection circuit, a first electrode coupled to thefirst power line, and a second electrode coupled to the second powerline, for providing a discharge path between the first and second powerlines when the control terminal receives the enable signal.
 12. Thedisplay panel as claimed in claim 11, wherein the ESD detection circuitcomprises: a resistor having a first terminal coupled to the first powerline; and a capacitor having a first terminal coupled to a secondterminal of the resistor and a second terminal coupled to the secondpower line.
 13. The display panel as claimed in claim 12, wherein thedischarge device is a P-type thin film transistor with a gate coupled tothe second terminal of the resistor, a source coupled to the first powerline, and a drain coupled to the second power line.
 14. The displaypanel as claimed in claim 11, wherein the ESD detection circuitcomprises: a capacitor having a first terminal coupled to the firstpower line; and a resistor having a first terminal coupled to a secondterminal of the capacitor and a second terminal coupled to the secondpower line.
 15. The display panel as claimed in claim 14, wherein thedischarge device is an N-type thin film transistor with a gate coupledto the second terminal of the capacitor, a source coupled to the secondpower line, and a drain coupled to the first power line.
 16. The displaypanel as claimed in claim 14, wherein the ESD detection circuit furthercomprises an inverter disposed between the second terminal of thecapacitor and the control terminal of the discharge device.
 17. Thedisplay panel as claimed in claim 16, wherein the discharge device is aP-type thin film transistor with a gate coupled to the output of theinverter, a source coupled to the first power line, and a drain coupledto the second power line.
 18. The display panel as claimed in claim 11,wherein the ESD detection circuit comprises: a resistor having a firstterminal coupled to the first power line; a capacitor having a firstterminal coupled to a second terminal of the resistor and a secondterminal coupled to the second power line; a first P-type thin filmtransistor having a gate coupled to the second terminal of the resistor,a source coupled to the first power line, and a drain coupled to thecontrol terminal; and a second N-type thin film transistor having a gatecoupled to the second terminal of the resistor, a source coupled to thesecond power, and a drain coupled to the drain of the first P-type thinfilm transistor.
 19. The display panel as claimed in claim 18, whereinthe discharge device is an N-type thin film transistor with a gatecoupled to the to the output of the ESD detection circuit, a sourcecoupled to the first power line, and a drain coupled to the second powerline.
 20. The display panel as claimed in claim 19, wherein thecapacitor is a third N-type thin film transistor with a gate coupled tothe second terminal of the resistor and a source and drain coupled tothe second power line.